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May 1997
ML2264* 4-Channel High-Speed 8-Bit A/D Converter with T/H (S/H)
GENERAL DESCRIPTION
The ML2264 is a high-speed, P compatible, 4-channel 8-bit A/D converter with a conversion time of 680ns over the operating temperature range and supply voltage tolerance. The ML2264 operates from a single 5V supply and has an analog input range from GND to VCC. The ML2264 has two different pin selectable modes. The T/H mode has an internal track and hold. The S/H mode has a true internal sample and hold and can digitize 0 to 5V sinusoidal signals as high as 500kHz. The ML2264 digital interface has been designed so that the device appears as a memory location or I/O port to a P. Analog input channels are selected by the latched and decoded multiplexer address inputs. The ML2264 is an enhanced, pin compatible second source for the industry standard AD7824. The ML2264 enhancements are faster conversion time, parameters guaranteed over the supply tolerance and temperature range, improved digital interface timing, superior power supply rejection, and better latchup immunity on analog inputs.
FEATURES
s
s s s s s s s s s s s s s
Conversion time, WR-RD mode over temperature and supply voltage tolerance Track & Hold Mode ................................. 830ns max Sample & Hold Mode .............................. 700ns max Total unadjusted error ..................... 1/2 LSB or 1 LSB Capable of digitizing a 5V, 250kHz sine wave 4-analog input channels No missing codes 0V to 5V analog input range with single 5V power supply No zero or full scale adjust required Analog input protection ............................... 25mA min Operates ratiometrically or with up to 5V voltage reference No external clock required Power-on reset circuitry Low power ....................................................... 100mW Narrow 24-pin DIP, SOIC, or SSOP Superior pin compatible replacement for AD7824
BLOCK DIAGRAM
VCC +VREF SH/TH +VREF 4-BIT FLASH A/D (MSB) DECODE LOGIC, LATCH & THREE STATE OUTPUT BUFFER -VREF GND
PIN CONNECTIONS
24-Pin DIP
A IN 4 A IN 3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
24-Pin SOIC 24-Pin SSOP
VCC A IN 4 SH/TH IN 3 A A0 A IN 2 A1 DB6 DB5 DB4 CS
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
VCC SH/TH A0 A1 DB7 DB6 DB5 DB4 CS WR/RDY +VREF -VREF
-VREF A IN 1 A IN 2 A IN 3 A IN 4 4-CH MUX SAMPLE & HOLD - + +VREF -VREF +VREF 16
A IN 2 A IN 1 MODE DB0 DB1 DB2 DB3 RD INT GND
A IN 1 DB0 DB1 DB2
DB7 MODE
4-BIT D/A
-VREF 16
4-BIT FLASH A/D (LSB) TIMING & CONTROL INT
DB3 WR/RDY RD
+VREF INT -VREF GND
ADDRESS LATCH DECODE A0 A1
TOP VIEW
TOP VIEW
CS WR/RDY RD SH/TH MODE
*This Part Is End Of Life As Of August 1, 2000
1
ML2264
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1 2 3 4 5
A IN 4 A IN 3 A IN 2 A IN 1 MODE
Analog input 4. Analog input 3. Analog input 2. Analog input 1. Mode select input. MODE = GND: RD mode MODE = VCC: WR-RD mode Pin has internal current source pulldown to GND. Data output -- bit 0 (LSB). Data output -- bit 1. Data output -- bit 2. Data output -- bit 3. Read input. In RD mode, this pin initiates a conversion. In WR-RD mode, this pin latches data into output latches. See Digital Interface section. Interrupt output. This output signals the end of a conversion and indicates that data is valid on the data outputs. See Digital Interface section. Ground. Negative reference voltage for A/D converter. Positive reference voltage for A/D converter.
15 WR/RDY
Write input or ready output. In WR-RD mode, this pin is WR input. In RD mode, this pin is RDY open drain output. See Digital Interface section. Chip select input. This pin must be held low for the device to perform a conversion. Data output -- bit 4. Data output -- bit 5. Data output -- bit 6. Data output -- bit 7 (MSB). Digital address input 1 that selects analog input channel. See multiplexer addressing section. Digital address input 0 that selects analog input channel. See multiplexer addressing section. S/H, T/H mode select. When SH/TH = VCC, the device is in sample and hold mode. When SH/TH = GND, the device is in track and hold mode. Pin has internal pulldown current source to GND. Positive supply. +5 volts 5%.
16 CS
17 DB4 18 DB5 19 DB6 20 DB7 21 A1
6 7 8 8
DB0 DB1 DB2 DB3
10 RD
22 A0
23 SH/TH
11 INT
12 GND 13 -VREF 14 +VREF
24 VCC
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage, VCC ................................................. 6.5V Voltage Logic Inputs ................................. -0.3V to VCC + 0.3V Analog Inputs .............................. -0.3V to VCC + 0.3V Input Current per Pin (Note 2) .............................. 25mA Storage Temperature .............................. -65C to +150C Package Dissipation at TA = 25C (Board Mount) ............................. 875mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Plastic) ............................ 260C Dual-In-Line Package (Ceramic) ......................... 300C SOIC Vapor Phase (60 sec.) ..................................... 215C Infrared (15 sec.) ............................................ 220C
OPERATING CONDITIONS
Supply Voltage, VCC ............................ 4.5VDC to 6.0VDC Temperature Range (Note 3) ................. TMIN - TA - TMAX ML2264CCS ML2264CCP ML2264CCR ........................................... 0C to +70C
2
ML2264
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = +VREF = 5V 5%, and -VREF = GND (Note 1)
ML2264XCX PARAMETER Converter Total Unadjusted Error ML2264CXX Integral Linearity Error ML2264CXX Differential Linearity Error ML2264CXX Full Scale Error ML2264CXX Zero Scale Error ML2264CXX Channel to Channel Mismatch +VREF Voltage Range -VREF Voltage Range Reference Input Resistance Analog Input Range Power Supply Sensitivity 4, 6 4, 6 4 4 4 4 5 5 4 4, 7 4 DC VCC =5V 5%, VREF = 4.50V 100mVp-p 100kHz sine on VCC, VIN = 0 Analog Input Leakage Current, OFF Channel 4 ON Channel = VCC OFF Channel = 0V ON Channel = 0V OFF Channel = VCC Analog Input Leakage Current, ON Channel 4 ON Channel = 0V OFF Channel = VCC ON Channel = VCC OFF Channel = 0V Analog Input Capacitance Digital and DC VIN(1), Logical "1" Input Voltage VIN(0), Logical "0" Input Voltage IIN(1), Logical "1" Input Current IIN(0), Logical "0" Input Current 4 WR, RD, CS, A0, A1 MODE, SH/TH 4 WR, RD, CS, A0, A1 MODE, SH/TH 4 VIH = VCC VIL = GND WR, RD, CS, A0, A1 MODE, SH/TH 4 WR, RD, CS MODE, SH/TH 15 -1 -20 50 2.0 VCC-0.5 0.8 0.5 1 150 V V V V A A A A During Acquisition Period 45 -1 1 -1 1 -VREF GND-0.1 1 GND-0.1 1/32 1/16 2.5 1 1 1 1 1 1/4 VCC+0.1 +VREF 4 VCC+0.1 1/4 LSB LSB LSB LSB LSB LSB V V ky V LSB LSB A A A A pF NOTES CONDITIONS MIN TYP (NOTE 3) MAX UNITS
3
ML2264
ELECTRICAL CHARACTERISTICS (Continued) Unless otherwise specified, TA = TMIN to TMAX, VCC = +VREF = 5V 5%, and -VREF = GND, and timing measured at 1.4V, CL = 100pF. (Note 1)
ML2264XCX PARAMETER Digital and DC (Continued) VOUT(1), Logical "1" Output Voltage VOUT(0), Logical "0" Output Voltage IOUT, Three-State Output Current COUT, Logic Output Capacitance CIN, Logic Input Capacitance ICC, Supply Current 4 CS = WR = RD = "1", No Output Load 4 4 4 IOUT = -2mA IOUT = 2mA VOUT = 0V VOUT = VCC 5 5 18 -1 4.0 0.4 V V A 1A pF pF mA NOTES CONDITIONS MIN TYP (NOTE 3) MAX UNITS
AC and Dynamic Performance (Note 9) tCRD, Conversion Time, Read Mode tCWR-RD, Conversion Time, Write-Read Mode 4 4, 8 RD to INT, MODE = 0V WR Falling Edge to INT, tRD < tINT, MODE = VCC SH/TH = VCC SH/TH = GND 48 1020 700 830 ns ns ns dB
SNR, Signal to Noise Ratio
VIN = 5V, 250kHz Noise is sum of all nonfundamental components from 0-500kHz. SH/TH = VCC, MODE = VCC fSAMPLING = 1.0 MHz VIN = 5V, 250kHz THD is sum of 2-5th harmonics relative to fundamental. SH/TH = VCC, MODE = VCC fSAMPLING = 1.0 MHz fa = 2.5V, 250kHz fb = 2.5V, 248kHz IMB is (fa + fb), (fa - fb), (2fa + fb), (2fa - fb), (fa + 2fb), or (fa - 2fb) relative to fundamental. SH/TH = VCC, MODE = VCC fSAMPLING = 1.0 MHz VIN = 5V, 0-250kHz Relative to 1kHz SH/TH = VCC, MODE = VCC fSAMPLING = 1.0 MHz 5 SH/TH = VCC SH/TH = GND SH/TH = GND, Figure 1 (Track & Hold Operation) 0
HD, Harmonic Distortion
-63
dB
IMD, Intermodulation Distortion
-60
dB
FR, Frequency Response
0.1
dB
SR, Slew Rate Tracking
4.0 0.25
V/s V/s ns
tAS, Multiplexer Address Setup Time
4
4
ML2264
ELECTRICAL CHARACTERISTICS
(Continued) Unless otherwise specified, TA = TMIN to TMAX, VCC = +VREF = 5V 5%, and -VREF = GND, and timing measured at 1.4V, CL = 100pF. (Note 1)
ML2264XCX PARAMETER NOTES CONDITIONS MIN TYP (NOTE 3) MAX UNITS
AC and Dynamic Performance (Note 9) (Continued) tAH, Multiplexer Address Hold Time tAS, Multiplexer Address Setup Time tAH, Multiplexer Address Hold Time 4 4 4 SH/TH = GND, Figure 1 (Track & Hold Operation) SH/TH = VCC, Figure 2 (Sample & Hold Operation) SH/TH = VCC, Figure 2 (Sample & Hold Operation) 60 225 60 ns ns ns
AC Performance Read Mode (Pin 5 = 0V), Figure 4 tRDY, CS to RDY Delay tRDD, RD Low to RDY Delay tCSS, CS to RD, WR Setup Time tCSH, CS to RD, WR Hold Time tCRD, Conversion Time -- RD Low to INT low tACC0, Data Access Time RD to Data Valid tRDPW, RD Pulse Width tINTH, RD to INT Delay tDH, Data Hold Time -- RD Rising Edge to Data High Impedance State tP, Delay Time Between Conversions -- INT Low to RD Low 4 4, 9 4 4 4, 9 4 4 4, 9 5, 9 Figure 3 tCRD-10 tCRD+30 0 0 65 50 Figure 3 0 0 1020 tCRD+20 0 60 1020 ns ns ns ns ns ns ns ns ns
4, 9
Sample & Hold Mode, SH/TH = VCC Track & Hold Mode, SH/TH = GND
300 240
ns ns
AC Performance Write-Read Mode (Pin 5 = 5V), Figures 5 and 6 tCSS, CS to RD, WR Setup Time tCSH, CS to RD, WR Hold Time tWR, WR Pulse Width tRD, Read Time -- WR High to RD Low Delay tRI, RD to INT Delay tACC1, Data Access Time -- RD Low to Data Valid tCWR-RD, Conversion Time -- WR Falling Edge to INT Low 4 4 4 5 4 4, 9 4 4, 8, 9 5, 8, 9 SH/TH = VCC SH/TH = GND tRD < tINTL tRD < tINTL tRD < tINTL tRD < tINTL, SH/TH = VCC tRD < tINTL, SH/TH = GND 0 0 190 320 275 0 0 235 240 700 830 50K 50K ns ns ns ns ns ns ns ns ns
5
ML2264
ELECTRICAL CHARACTERISTICS (Continued) Unless otherwise specified, TA = TMIN to TMAX, VCC = +VREF = 5V 5%, and -VREF = GND, and timing measured at 1.4V, CL = 100pF. (Note 1)
ML2264XCX PARAMETER NOTES CONDITIONS MIN TYP (NOTE 3) MAX UNITS
AC Performance Write-Read Mode (Pin 5 = 5V) Figures 5 and 6 (Continued) tINTL, Internal Comparison Time -- WR Rising Edge to INT Low tACC2, Data Access Time -- RD to Data Valid tDH, Data Hold Time -- RD Rising Edge to Data High Impedance State tINTH, RD to INT Delay tP, Delay Time Between Conversions -- INT Low to WR Low 4, 9 tRD > tINTL 620 ns
4 5, 9
tRD > tINTL Figure 3
0 0
50 50
ns ns
4, 9 4, 9 Sample & Hold Mode, SH/TH = VCC Track & Hold Mode, SH/TH = GND 4, 9 4, 9 Standalone Mode Standalone Mode
0 300 240 0 0
65
ns ns ns
tIHWR, WR to INT Delay tID, INTO to Data Valid Delay
Note Note Note Note Note Note 1: 2: 3: 4: 5: 6:
90 20
ns ns
Note 7:
Note 8: Note 9:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. When the voltage at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA or less. Typicals are parametric norm at 25C. Parameter guaranteed and 100% production tested. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. Total unadjusted error includes offset, full scale, linearity, sample and hold, and multiplexer errors. Total unadjusted error is tested at the minimum specified times for WR, RD, tR1, and tP. For example, for the ML2264XCX in the sample and hold mode, WR/RD mode: tWR = 190ns, tRD = 275ns with a frequency of 1.000MHz (cycle time of 1000ns). For -VREF * VIN the digital output code will be 0000 0000. Two on-chip diodes are tied to the analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct -- especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allows 100mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading. Conversion time, write-read mode = tWR + tRD + tRI. Defined from the time an output crosses 0.8V or 2.4V.
6
ML2264
A0, A1 ADDR VALID tAH tAS RD WR tAS A0, A1 ADDR VALID tAH
a) RD Mode (Pin 5 = GND)
b) WR-RD Mode (Pin 5 = VCC)
Figure 1. Analog Multiplexer Address Timing for Track & Hold Mode (Pin 23 = GND)
CS tAS tAH A0, A1 ADDR VALID
Figure 2. Analog Multiplexer Address Timing for Sample & Hold Mode (Pin 23 = VCC)
tf DATA OUTPUT 10pF 5k OUTPUT GND OUTPUT ENABLE VCC GND VOH 50% 10% 90%
t1H VOH - 100mV
VCC OUTPUT ENABLE VCC GND VCC OUTPUT VOL
tf 50% 10% 90%
5k DATA OUTPUT 10pF
t0H VOL + 100mV
Figure 3. High Impedance Test Circuits and Waveforms
7
ML2264
CS tCSH tRDPW RD tCSS tRDD WITH EXTERNAL PULL-UP tRDY INT tCRD DB0-DB7 tACC0 VALID DATA tDH DB0-DB7 tACC1 VALID DATA tDH tINTH INT tINTH WR tP tCSS RD tRI tWR tRD tP CS tCSH
RDY
*In SAMPLE & HOLD mode a pull up resistor on RDY should not be used unless CSO is * 20ns before RDO.
Figure 6. WR-RD Mode Timing (tRD < tINTL)
Figure 4. RD Mode Timing
CS
tINTL
WR tCSS RD
tWR tCSH tP tRD
WR tWR
tIHWR
tP
tINTH
INT tID
INT tINTL DB0-DB7 tACC2 tDH VALID DATA
DB0-DB7
VALID DATA
Figure 7. WR-RD Mode Stand-Alone Timing CS = RD = 0 Figure 5. WR-RD Mode Timing (tRD > tINTL)
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ML2264
1.0 FUNCTIONAL DESCRIPTION
The ML2264 uses a two stage flash technique for A/D conversion. This technique first performs a 4 bit flash conversion on VIN to determine the 4 MSB's. These 4 MSB's are then cycled through an internal DAC to recreate the analog input. This reconstructed analog input signal from the DAC is then subtracted from the input, and the difference voltage is converted by a second 4 bit flash conversion, providing the 4 LSB's of the output data word. 1.1 MULTIPLEXER ADDRESSING The ML2264 contains a 4-channel single ended analog multiplexer. A particular input channel is selected by using the address inputs A0 and A1. The relationship between the address inputs, A0 and A1, and the analog input selected is shown in Table 1. Selected Analog Channel A IN 1 A IN 2 A IN 3 A IN 4 Address Input A0 0 1 0 1 A1 0 0 1 1 The equivalent input circuit for the converter is shown in Figure 8. When the conversion starts in the T/H mode (WRO in the WR-RD mode or RDO in the RD mode) S1, S4 and S6 close and S3 opens. This period is known as the acquisition period where the MSB flash converter tracks the input signal and the LSB flash converter samples it. During this period, VIN is connected to the 16 MSB and 15 LSB comparators. Thus 38pF of input capacitance must be charged up through the combined RON resistance of the internal analog switches plus any external source resistance, RS. In addition, there is a stray capacitance of approximately 11pF that needs to be charged through the external source resistance RS. This period ends in the WRRD mode when WR or by an internal timer in the RD mode. At this point S1 and S4 open and the analog input at VIN is no longer being sampled; thus during this time the analog voltage on VIN does not affect converter performance. As shown above, the critical period for charging up the analog input occurs when the MSB and LSB comparators are sampling the input, known as the acquisition period. The source of the external signal on VIN must adequately charge up the analog voltage during the acquisition period. To do this, the input must settle within the required analog accuracy tolerance at least 50ns before the end of the acquisition period so that the MSB comparators have adequate time to make the correct decision. If more time is needed due to finite charging or settling time of the external source, the WR low period can be extended in WR-RD mode. In RD mode, since the acquisition time is fixed by internal delays, the burden is on the external source to charge up and settle the input adequately. When the ML2264 operates in the S/H mode (pin 23 = VCC) both the MSB and the LSB flash converter perform a true sample and hold operation during the acquisition or sampling period. This period starts after the falling edge of INT and ends with the falling edge of WR in the WR-RD mode or the falling edge of RD in the RD mode. The duration of this period is user controlled and must satisfy a minimum of tP. During this period S1, S3, S4 and S6 close, therefore 46pF of input capacitance must be charged up in addition to the 11pF of stray capacitance. 1.3 TRACK AND HOLD vs. SAMPLE AND HOLD The MSB Flash Converter of the ML2264 in T/H mode has a track and hold mechanism for sampling the input. The input is attached to the MSB comparators directly in the MSB compare cycle, or acquisition period. When the MSB compare cycle ends, the state of the MSB comparators is latched. The LSB Flash Converter always performs a S/H operation. Thus, the analog input signal can be changing during the MSB compare cycle, or acquisition period, and
Table 1. Multiplexer Address Decoding The address inputs are latched into the ML2264 on the falling edge of the RD, WR, or CS depending on the state of pins SH/TH and mode as shown in Table 2. Address Latching Signal RDO WRO CSO CSO
Mode GND VCC GND VCC Table 2.
Operation Mode GND GND VCC VCC
In the Sample & Hold mode of operation CS is used as the address latch enable, allowing for continuous conversions without addressing a given analog input for each conversion. The Track & Hold mode of operation requires an analog input to be addressed and latched for each conversion that the ML2264 performs. 1.2 ANALOG INPUTS The analog input on the ML2264 behaves differently than inputs on conventional converters. The analog input current requirements change while the conversion is in progress, and the amount of input current depends on what cycle the converter is in.
9
ML2264
the MSB comparators will be tracking it as long as the slew rate of the analog input is slow enough so that the MSB comparators can respond. The ML2264 can track and hold signals with slew rates as high as 0.25V/s (16kHz @ 5 volts) without sacrificing conversion accuracy. The ML2264 in S/H mode does not have the slew rate limitation of the T/H mode since an internal sample and hold acquires the analog signal, holds it internally, and then performs a conversion. Since this is a true sample and hold function, the S/H mode can theoretically digitize signals of frequencies much higher than the T/H mode. The ML2264 in S/H mode can digitize signals of frequencies as high as 250kHz @ 5V (slew rates as high as 4V/s) without sacrificing conversion accuracy. In most applications, the S/H mode is more desirable than T/H mode because of the better dynamic performance. 1.3.1 Converter -- T/H Mode The operating sequence for the WR-RD mode is illustrated in Figure 9a. Initially, the internal comparators are autozeroed while WR is high. A conversion is initiated by the falling edge of WR. While WR is low, the MSB comparators are tracking the analog input and comparing this voltage against voltages from the internal resistor ladder. At the same time, the input is being acquired or sampled by LSB comparators. On the rising edge of WR, the MSB comparator results are latched, and the LSB acquisition time is ended by closing the sampling switch to the LSB comparators. While WR is high, the LSB comparators then compare the residual input voltage against internal voltages from the resistor ladder to determine the 4 LSB's. When the LSB comparison or conversion is complete, INT goes low and latches the conversion result into the output latches. Then, the comparators are auto-zeroed while WR is high before another conversion can start. The operating sequence for RD mode, is similar to that described above for the WR-RD mode, except the conversion is initiated by the falling edge of RD, and the MSB and LSB conversions are generated by internal clock edges that are generated while RD is low.
11pF RS RON 4K TO MS LADDER S1 1pF 1pF S2 1.2K RON S3
VIN
16 MSB COMPARATORS
RON 6.4K TO LS LADDER
S4
1.34pF 1pF 3.6K RON S6
S5
0.65pF
15 LSB COMPARATORS
Figure 8. Converter Equivalent Input Circuit 1.3.2 Converter -- S/H Mode The operating sequence for S/H mode is illustrated in Figure 9b. Notice that it is similar to T/H mode described above except this mode has a true sample and hold function. The falling edge of INT closes the sampling switch and starts the acquisition period where the analog input is sampled at the same time all comparators are auto-zeroed. The falling edge of WR opens the internal sampling switch, ends the acquisition period, and starts the conversion on the internally sample and held signal. The MSB comparators make their decisions while WR is low. On the rising edge of WR, the MSB comparator results are latched. The LSB comparators make their decision when WR is high. When the LSB comparison or conversion is complete, INT goes low and latches the conversion result into the output buffers. Then, the acquisition period begins again and the converter is ready for the next conversion. The operating sequence for the RD mode is the same as the WR-RD mode, except the conversion is initiated by the falling edge of RD, and the MSB and LSB conversions are generated by internal clock edges that are generated while RD is low.
10
ML2264
(a) S/H Mode
WR
ACQUISITION OR SAMPLING PERIOD. ALL COMPARATORS AUTOZEROED.
MSB COMPARATORS DECIDING.
LSB COMPARATORS DECIDING.
CONVERSION STARTS. VIN SAMPLING ENDS. HOLD TIME STARTS.
MSB COMPARATOR RESULTS ARE LATCHED.
RD BROUGHT LOW LATCHES LSB COMPARATOR RESULTS AND BRINGS INT LOW.
(a) T/H Mode
WR
ALL COMPARATORS AUTOZEROED.
ACQUISITION PERIOD. MSB COMPARATORS ARE TRACKING VIN. LSB COMPARATORS ARE SAMPLING VIN.
LSB COMPARATORS DECIDING.
CONVERSION STARTS.
VIN SAMPLING ENDS. MSB COMPARATOR RESULTS ARE LATCHED.
RD BROUGHT LOW LATCHES LSB COMPARATOR RESULTS AND BRINGS INT LOW.
Figure 9. Operating Sequence (WR-RD Mode) 1.4 REFERENCE The +VREF and -VREF inputs are the reference voltages that determine the full scale and zero input voltages, respectively, for the A/D converter. Thus, +VREF defines the analog input which produces a full scale output and -VREF defines the analog input which produces an output code of all zeroes. The transfer function for the A/D converter is shown in Figure 10. +VREF and -VREF can be set to any voltage between GND and VCC. This means that the reference voltages can be offset from GND and the difference between +VREF+ and -VREF- can be made small to increase the resolution of the conversion. Note that the total unadjusted error increases when [+VREF - (-VREF)] decreases. 1.5 POWER SUPPLY AND REFERENCE DECOUPLING A 0.1F ceramic disc capacitor is recommended to bypass VCC to GND, using as short a lead length as possible. If REF+ and REF- inputs are driven by long lines, they should be bypassed by 0.1F ceramic disc capacitors at the reference input pins.
OUTPUT CODE FULL SCALE TRANSITION
11111111 11111110 11111101
00000011 00000010 00000001 00000000
1LSB
2LSB'S
3LSB'S
0
FS FS - 1LSB
AIN, INPUT VOLTAGE (IN TERMS OF LSB'S)
Figure 10. A/D Transfer Characteristic
11
ML2264
1.6 DYNAMIC PERFORMANCE 1.6.1 Sinusoidal Inputs Since the ML2264 has an internal sample and hold, the device can digitize high frequency sinusoids with little or no signal degradations. Using the Nyquist criteria, the highest frequency input to the converter could theoretically be 1/2 the sampling rate (fS). Any frequency components above fS/2 will be aliased below fS/2. In most applications, these aliased components cause unacceptable distortion and must be filtered out of the input. If the input frequency is too close to fS/2, then the requirements on the anti-alias filter become difficult to impossible to realize with standard component and tolerances. In most practical applications, the highest input frequency has to be limited to 1/3 to 1/4 of fMAX in order to relax the filtering requirements enough to make a realizable anti-alias filter. The maximum sampling rate (fmax) for the ML2264 in the WR-RD mode, (tRD < tINTL) can be calculated as follows: fmax = fmax = t WR + tRD + tRI + tP 1 190ns + 275ns + 235ns + 300ns 1 In applications where aliased frequency components are acceptable and filtering of the input signal is not needed, or where a filter with a steep amplitude response is available, the user can apply an input sinusoid higher than 250kHz to the device. Note, however, that as the input frequency increases above 500kHz, dynamic performance degradation will occur due to the finite bandwidth of the internal sample and hold. The Figure 11 plots are 4096 point FFT's of the ML2264 converting a 257kHz and a 491kHz, 0 to 4.5V, low distortion sine wave input. The ML2264 samples and digitizes at its specified accuracy, dynamic input signals with frequency components up to the Nyquist frequency (one-half the sampling rate). The output spectra yields precise measure-ments of the input signal level, harmonic components, and signal to noise ratio up to the 8-bit level. The near ideal signal to noise ratio is maintained independent of increasing analog input frequencies to 500kHz. 1.6.2 Signal-To-Noise Ratio Signal-to-noise ratio (SNR) is the measured signal to noise at the output of the converter. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more the levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92 dB. 1.6.3 HARMONIC DISTORTION Harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2264 is defined as
fmax = 1.000 MHz tWR = Write Pulse Width tRD = Delay Time between WR and RD Pulses tRI = RD to INT Delay tP = Delay Time between Conversions This permits a maximum sampling rate of 1MHz for the ML2264. The dynamic performance specifications (SNR, HD, IMD, and FR) for the ML2264 are all specified at 250kHz, which is approximately 1/4 of the sampling rate, fS.
0 -10 -20 -30 -40 SNR 48.4dB HD -62.87dB VCC = VREF = 5.0V TA = 25 C
0 -10 -20 -30 -40 SNR 49.1dB HD -58.33dB VCC = VREF = 5.0V TA = 25 C
MAGNITUDE (dB)
-50 -60 -70 -80 -90
MAGNITUDE (dB)
0 200 FREQUENCY (kHz) 400
-50 -60 -70 -80 -90 -100 -110 -120 0 200 FREQUENCY (kHz) 400
-100 -110 -120
a) Output Spectrum with fIN = 257kHz, fS = 1MHz
b) Output Spectrum with fIN = 491kHz, fS = 1MHz
Figure 11. Dynamic Performance, Sample and Hold Mode
12
ML2264
20 log (V2 + V3 + V4 + V5 )1 2 V1
2 2 2 2
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 are the rms amplitudes of the individual harmonics. 1.6.2 Signal-To-Noise Ratio Signal-to-noise ratio (SNR) is the measured signal to noise at the output of the converter. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more the levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92 dB. 1.6.3 HARMONIC DISTORTION Harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2264 is defined as
20 log (V2 + V3 + V4 + V5 )1 2 V1
2 2 2 2
on the falling edge of RD. While RD is low, the MSB and LSB decisions are made with internally generated clock edges. When the conversion is complete, RDY goes high and INT goes low signaling the end of the conversion. After INT goes low, the data outputs go from high impedance to active state with valid output data. Data stays valid until either RD or CS goes high. When either signal goes high, the output data lines return to the high impedance state and INT returns high. 1.7.2 WR-RD Mode In the WR-RD mode, the WR/RDY pin is configured as the WR input. In this mode, WR initiates the conversion and RD controls reading the output data. This can be done in several ways, described below. 1.7.3 WR-RD Mode -- Using Internal Delay (tRD > tINTL) The timing is shown in Figure 5. To do a conversion, CS must be low to select the device. Then, WR falling edge triggers the conversion. While WR is low, the MSB comparison is made. When WR returns high the LSB decision is made. After some internal delay, INT goes low indicating end of conversion. Valid data will appear on DB0-7 when RD is pulled low. INT is then reset by the rising edge of either CS or RD. 1.7.4 WR-RD Mode -- Reading Before Delay (tRD < tINTL) The internally generated delay for the LSB decision when tRD > tINTL is longer than necessary due to circuit design tolerances of tINTL delay. If desired, a faster conversion will result without loss of accuracy by bringing RD low within the minimum time specified for tRD. The timing diagram for this mode is shown in Figure 6. WR is the same as when tRD > tINTL. But in this case, RD is brought low tRD ns after WR rising edge and before INT. INT goes low indicating an end of conversion after the falling edge of RD and is reset on the rising edge of RD or CS. When RD is brought low before INT goes low the data bus always remains in the high-impedance state until INTO. 1.7.5 WR-RD Mode -- Stand Alone Operation Stand alone operation can be implemented by tying CS and RD low as shown in Figure 7. WR initiates a conversion as before. When WR is low, the MSB comparison is made. When, WR goes high, the LSB comparison is made. Since RD is already low, the output data will appear automatically at end of conversion. Since RD is always low, INT is reset on rising edge of WR and goes low at end of conversion. 1.7.6 Power-On Reset When power is first applied, an internal power-on reset and timer circuit inhibits the CS input and resets the internal circuitry to prevent the ML2264 from starting in an unknown state. During this period of approximately 3s, INT remains high and the data bus is in the highimpedance state.
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 are the rms amplitudes of the individual harmonics. 1.6.4 Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfA + nfB, where m, n = 0, 1, 2, 3 ... Intermodulation terms are those for which m or n is not equal to zero. The (IMD) intermodulation distortion specification includes the second order terms (fA + fB) and fA - fB) and the third order terms (2fA + fB), (2fA - fB), (fA + 2fB), and (fA - 2fB) only. 1.7 DIGITAL INTERFACE The ML2264 has two basic interface modes, RD and WRRD, which are selected by the MODE input pin. 1.7.1 RD Mode In the RD mode, WR/RDY pin is configured as the RDY output. The read mode performs a conversion with a single RD pulse. This allows the P to start a conversion, wait, and then read data with a single read instruction. The timing for the RD mode is shown in Figure 4. To do a conversion, CS must be low to select the device. After CS goes low, the RDY output goes low indicating that the device is ready to do a conversion. The conversion starts
13
ML2264
2.0 TYPICAL APPLICATIONS
5V
68008 ML2264
+15VDC * + - * -15VDC AIN ML2264 VCC + 0.1F
CS A0 A1 INT RD DB7 DB0 DATA
ADDRESS DECODE
AS
DTACK R/W
*NO PROTECTION REQUIRED IF INPUT CURRENT <25mA
Figure 12. Protecting the Input
DB7 DB0
Figure 15. 68000 Type Interface to ML2264
0 VIN VCC
ML2264 VCC AIN +VREF
5V + 0.1F
50K
5V
25K ML2264
-VREF GND
VIN - +
A IN 1 A IN 2 A IN 3 A IN 4
Figure 13. Using VCC as Reference for Ratiometric Operation Figure 16. 2.5V Analog Input Range
12V +VREF + 0 VIN 4.5 ML2264 4.50V 0.1F P
VREFOUT VCC ML2340 D/A WITH REFERENCE
ML2264 A IN 1 A IN 2 A IN 3 A IN 4 CS A0 A1 WR RD INT DB7 DB0 DATA
8051 P3, 1 P3, 2 P3, 3 P3, 4 P3, 5 P3, 6 P1, 7 P1, 0
VOUT
Figure 14. Using External Reference of D/A
Figure 17. 8051 Interface to ML2264
14
ML2264
2.0 TYPICAL APPLICATIONS
(Continued)
DB7 DB0 A IN 1 A IN 2 A IN 3 A IN 4 INT RD A0 A1 ML2264 WR CS CLOCK SOURCE OR TIMER VOUT
DATA
DB7 DB0 INT DEN
ADDRESS DECODE DB7 DB0 ML2341 D/A CS WR
HEN TMS320 /E14 C15 PA0 PA1 PA2 WE
Figure 18. TMS320 Interface with D/A Output
VCC (5VDC)
4k
- + FS ADJ + 0.85VCC 0.1F ML2264 A IN 1 A IN 2 A IN 3 A IN 4 +VREF VCC + 0.1F
1k 24k
ANALOG SOURCES 20k
- + ZERO ADJ + 0.15VCC 0.1F -VREF
1k 3k
Figure 19. Operating with a Ratiometric Analog Signal of 15% of VCC to 85% of VCC
15
ML2264
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P24N 24-Pin Narrow PDIP
1.240 - 1.260 (31.49 - 32.01) 24
PIN 1 ID
0.240 - 0.270 0.295 - 0.325 (6.09 - 6.86) (7.49 - 8.26)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S24 24-Pin SOIC
0.600 - 0.614 (15.24 - 15.60) 24
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
16
ML2264
PHYSICAL DIMENSIONS
inches (millimeters) (Continued)
Package: R24 24-Pin SSOP
0.318 - 0.328 (8.08 - 8.33) 24
0.205 - 0.213 (5.20 - 5.40) PIN 1 ID
0.301 - 0.313 (7.65 - 7.95)
1 0.026 BSC (0.65 BSC) 0.068 - 0.078 (1.73 - 1.98) 0 - 8
0.066 - 0.070 (1.68 - 1.78)
0.009 - 0.015 (0.23 - 0.38)
SEATING PLANE
0.002 - 0.008 (0.05 - 0.20)
0.022 - 0.038 (0.55 - 0.95)
0.004 - 0.008 (0.10 - 0.20)
ORDERING INFORMATION
PART NUMBER ML2264CCP (Obsolete) ML2264CCS (End Of Life) ML2264CCR (Obsolete) TOTAL UNADJUSTED ERROR 1 LSB TEMPERATURE RANGE 0C to +70C 0C to +70C 0C to +70C PACKAGE Molded DIP (P24) Molded SOIC (S24) Molded SSOP (R24)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS2264-01
17

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